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Architecture for Simultaneous Coding and Encryption Using Chaotic Maps

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Executive Summary

In this paper, the authors discuss an interpretation of arithmetic coding using chaotic maps. They present a hardware implementation using 64 bit fixed point arithmetic on Virtex- 6 FPGA (with and without using DSP slices). The encoder resources are slightly higher than a traditional AC encoder, but there are savings in decoder performance. The architectures achieve clock frequency of 400-500 MHz on Virtex-6 xc6vlx75 device. Arithmetic coding is a data compression technique that encodes data by creating a code string which represents a fractional value on the interval (0, 1).

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