Hardware

Assembler Design Techniques for a Reconfigurable Soft-Core Processor

Date Added: Jun 2014
Format: PDF

The reconfigurable processor design which utilizes platform such as Field Programmable Gate Array (FPGA) has offered several advantages in minimizing the non-recurring engineering cost and to reduce the time-to-market for processor-based products. However, when any modification is made to the processor architecture, the same information needs to be relayed to the assembler in order to generate the correct object files. This paper presents the assembler design techniques for a reconfigurable Reduced Instruction Set Computer (RISC) processor called UTeMRISC03.