Automatic IP Core Generation in SoC

Date Added: Nov 2009
Format: PDF

This paper presents performance comparison of two different techniques namely System generator for DSP (Sysgen) and HDL method in Embedded Development Toolkit (EDK) for developing a configurable optimized IP core for signal processing applications. This is performed by implementing and integrating the core in Xilinx System on Chip (SoC) platform with a target board of Xilinx Virtex-II Pro XC2VP30 FPGA. These methodologies are compared by taking case study of Distributed Arithmetic FIR (DAFIR) filter, and Fast Fourier Transform (FFT) IP core. The HDL method gives better performance in terms of logic resources and timing, but the generation and debugging of IP core consumes much time as compared to Sysgen method