Auxiliary Buffer Based Router Architecture for High End Traffic Behavior
The future demands for networking is the router architecture with adaptivity. Any router designing takes the parameters such as latency, throughput, power savings into account. Efficient buffer management is not only instrumental in the overall performance of the on-chip networks but also greatly affects the network energy consumption. To increase the quality of service in Network-on-Chips (NoCs) and to efficiently utilize the available hardware resources with high end traffic, This paper propose router architecture with auxiliary buffer and intelligent flow control mechanism. As applications show different traffic behavior at run-time, this solution allows one to obtain gains in throughput and latency under rather different communication loads, since the buffers slots are dynamically allocated to increase router efficiency in the NoC.