Bayesian Parameter Estimation Using Single-Bit Dithered Quantization
Analog-to-Digital Converters (ADCs) form an integral part of modern digital communication systems. However, with increasing bitrates, Analog-to-Digital (A/D) conversion becomes power-hungry, costly, and time-critical, especially at converter resolutions of 6-12 bits commonly employed today. Examples of such high-speed links include optical transceivers with electronic dispersion compensation for single-mode and multi-mode fiber, and chip-to-chip serial links. One approach to reduce the power consumption of ADCs operating at high speeds is to reduce their precision, since it becomes impractical to implement high resolution ADCs at any power budget as ADC speeds increase.