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In the scan-based Design For Testability (DFT) of Very Large Scale Integration (VLSI) circuits, the test responses of the circuits are observed after applying test patterns from the tester. All observed test responses are matched with fault-free test responses in order to pass the test. As the complexity and number of scan cells on a System-On-Chip (SOC) are rapidly increasing, using a single scan chain is becoming impractical in term of test time. However, the use of multiple scan chains has been limited by the number of tester channels. Achieving good test quality for a complex SOC, with the limited test access imposed by the finite number of tester input/output pins, poses a big challenge.
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