Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links

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Executive Summary

Clock and Data Recovery (CDR) circuits incorporating a bang-bang (BB) phase detector have been widely adopted in high-speed serial links due to their advantages in high speed implementations. However, the heavily nonlinear nature of the BB phase detector makes the analysis of the CDR loop difficult. This paper proposes a new technique for accurate and efficient estimation of the Bit Error Rate (BER) for BB CDR Circuits.

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