Date Added: Aug 2011
Future data centers will require novel, scalable memory architectures capable of sustaining high bandwidths while still achieving low memory access latencies. Electronic interconnects cannot meet the challenges presented by the need for multi-terabit off-chip memory data paths. In this paper, the electronic bus between main memory and its host processor is replaced with a circuit-switched optical interconnection network. The authors investigate the impact of their optically connected memory system on large-scale architectures and experimentally validate the protocol using field-programmable gate array based processor nodes and a custom-designed memory controller.