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This paper describes Cache Equalizer (CE), a novel distributed cache management scheme for large-scale Chip MultiProcessors (CMPs). The work is motivated by large asymmetry in cache sets' usages. CE decouples the physical locations of cache blocks from their addresses for the sake of reducing misses caused by destructive interferences. Temporal pressure at the on-chip last-level cache is continuously collected at a group (comprised of cache sets) granularity, and periodically recorded at the memory controller to guide the placement process.
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