Hardware

Cachecompression Techniques

Free registration required

Executive Summary

The proliferation of Chip MultiProcessors (CMPs) has led to the integration of large on-chip caches. With increasing number of cores and cache banks integrated on a single die, the on-chip network introduces significant communication latency and power consumption. Compression at cache level has capacity to improve performance by decreasing cache misses and increasing the effective bandwidth by transmitting compressed data. The speed of the microprocessors is being increasing faster than the speed of off-chip memory. Accessing off-chip memory takes more time than accessing an on-chip cache, and some more time to execute an instruction.

  • Format: PDF
  • Size: 635.7 KB