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The performance-cost benefits enjoyed for decades due to the scaling of device area are challenged by power and reliability constraints. Fixed power envelopes and increases in static and dynamic variations have lead to higher probability of parametric and wear-out failures. This is particularly true for processor memory arrays, such as caches, that dominate the area of modern processors and are built with minimum sized SRAM cells that are prone to failure. It is, therefore, becoming essential to develop scalable cost-effective fault-tolerant techniques for processor memory arrays.
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