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Many-core chips are emerging as the architecture of choice to provide power-scalability and improve performance while riding the Moore's law. On-chip interconnects are increasingly playing a pivotal role in power- and performance-scalability of such micro-architectures. As supply voltages begin to level off in future technologies, chip designs in general and interconnects in particular are resorting to specialization to provide power- and performance-scalability. In this paper, the authors make the observation that cache-coherent many-core chips exhibit a duality in on-chip network traffic. Request traffic typically consists of control packets requiring narrow low-power switches, while response traffic often carries cache block-sized payloads that require wider and higher-power switches.
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