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Cryptographic circuits need a special test infrastructure due to security constraints. Typical Design For Testability (DFT) methods, such as scan chains, as applied to most ASICs can not be applied directly to cryptographic chips. These methods, though providing the highest testability, open backdoors or side-channels for attackers to extract secret keys or Intellectual Property information from the core. Past approaches at secure test modified the existing design or on-chip DFT structure and was not suited for System on Chip (SoC) integration testing. This paper seeks to address the tradeoff between security, testability and test area overhead by presenting a challenge-response based Secure Test Wrapper structure, suitable for testing IP cores in a SoC environment.
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