Characterization of a Novel Low-Power SRAM Bit-Cell Structure at Deep Sub-Micron CMOS Technology for Multimedia Applications
To meet the increasing demands for higher performance and low-power consumption in present and future System-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep Sub-Micron (DSM) technology, it is coming as challenges, e.g., leakage power, performance, data retention and stability issues. In this paper, the authors have proposed a novel low-stress SRAM cell, called as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold.