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CMPs are now in common use. Increasing core counts implies increasing demands for instruction and data. However, processor-memory bus throughput has not kept pace. As a result, cache misses are becoming increasingly expensive. Yet the performance benefits of using more cores limits the cache per core, and cache per process, increasing the importance of efficiently using cache. To alleviate the increasing scarcity of on-chip cache, the authors propose a cooperative and adaptive data compression and migration technique and validate it with detailed hardware synthesis and full-system simulation.
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