Clock and Data Recovery Circuit for 2.5Gb/s Burst-Mode Receiver

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Executive Summary

This paper describes a 2.5Gb/s CDR for asynchronous burst-mode data transmission, such as ATM-PON. A CDR employing gated-oscillators was designed and simulated using AlGaAs/GaAs HBT. The gated-oscillator consumes 1.12 W of power with a single - 7 V supply, and the differential output voltage swing is 0.9 Vp-p into 50 W external loads. The simulation result shows that the designed CDR can extract clock instantaneously within one bit for 2.5Gb/s burst data packets.

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