Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures

In this paper, the authors present a code compression and on-the-fly decompression scheme suitable for coarse-grain reconfigurable technologies. These systems pose further challenges by having an order of magnitude higher memory requirement due to much wider instruction words than typical VLIW/TTA architectures. Current compression schemes are evaluated. A highly efficient and novel dictionary-based lossless compression technique is implemented and compared against a previous implementation for a reconfigurable system. This paper looks at several conflicting design parameters, such as the compression ratio, silicon area, latency, and power consumption.

Provided by: Institute of Electrical & Electronic Engineers Topic: Storage Date Added: Dec 2008 Format: PDF

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