Hardware

Collision Timing Attack when Breaking 42 AES ASIC Cores

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Executive Summary

A collision timing attack which exploits the data-dependent timing characteristics of combinational circuits is demonstrated. The attack is based on the correlation collision attack presented at CHES 2010, and the timing attributes of combinational circuits when implementing complex functions, e.g., S-boxes, in hardware are exploited by the help of the scheme used in another CHES 2010 paper namely fault sensitivity analysis. Similarly to other side-channel collision attacks, the approach avoids the need for a hypothetical model to recover the secret materials.

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