Comparative Analysis of Different Area Efficient FIR Filter Structures for Symmetric Convolutions

A comparative analysis based on speed vs area is done on parallel, serial and cascade serial FIR filter architectures and a DTMF test bench is also generated to test the architectures for various input frequencies. The VHDL code generated from MATLAB HDL code generator is synthesized in Xilinx ISE 14.2 and the various parameters which determine the speed and area efficiency of various architectures is tabulated and it is found out that for high speed operations parallel architecture is the best and for applications involving lot of computations where lot of speed is required serial architecture is well suited.

Provided by: International Journal of Electrical and Electronic Engineering & Telecommunications (IJEETC) Topic: Hardware Date Added: Apr 2014 Format: PDF

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