Comparative Study of 6T and 8T SRAM Using Tanner Tool
In this paper, the authors focus on the dynamic power dissipation during the write operation in CMOS SRAM cell. The charging and discharging of bit lines consume more power during the write "1" and Write "0" operation. 8T SRAM cell includes two more trail transistors in the pull down path for proper charging and discharging the bit lines. The results of 8T SRAM cell are taken on different frequencies at power supply of 1.5V. The circuit is characterized by using the 130nm technology which is having supply voltage of 1.5V.