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The Phase Detectors determines the relative phase difference between the two incoming signals and outputs a signal that is proportional to this phase difference. Some phase detectors also detect the frequency error, they are called Phase Frequency Detectors (PFD). It is very important block for the Delay Locked Loop. This paper presents the different design schemes of the PFD and compares them with their output results. The circuits that have been considered are the PFD using AND Gate, PFD using NOR Gate and PFD using NAND Gate. The different PFD circuits are designed and layouts are also simulated on Tanner EDA Tool using 0.18?m CMOS process technology with supply voltage 1.8V.
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