Hardware

Computation Vs. Memory Systems: Pinning Down Accelerator Bottlenecks

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Executive Summary

The world needs special-purpose accelerators to meet future constraints on computation and power consumption. Choosing appropriate accelerator architectures is a key challenge. In this paper, the authors present a pintool designed to help evaluate the potential benefit of accelerating a particular function. The tool gathers cross-procedural data usage patterns, including implicit dependencies not captured by arguments and return values. They then use this data to characterize the limits of hardware procedural acceleration imposed by on-chip communication and storage systems. Through an understanding the bottlenecks in future accelerator-based systems they will focus future research on the most performance-critical regions of the design. Accelerator designers will also find the tool useful for selecting which regions of their application to accelerate.

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