Hardware

Configurable M-Factor VLSI DVB-S2 LDPC Decoder Architecture With Optimized Memory Tiling Design

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Executive Summary

Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obtaining VLSI LDPC decoders that occupy small circuit areas and demand low power consumption, the authors propose in this paper a novel ASIC reconfigurable approach that exploits efficiently the memory block reshaping required to use a reduced number of processor nodes. They exploit different memory tiling configurations to reduce the memory area about 20%.

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