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Floating point operations are hard to implement on FPGAs i.e. on reconfigurable hardware's because of their complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high level of accuracy in their calculations. Therefore, VHDL programming for IEEE single precision floating point multiplier module have been explored. Various parameters i.e. combinational delay (Latency), chip area (number of slices used), modeling formats, memory usage etc have been analyzed while implementing the floating point multiplier on Spartan 2E module. Floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers.
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