Continuous Reliability Monitoring Using Adaptive Critical Path Testing

As processor reliability becomes a first order design constraint, this research argues for a need to provide continuous reliability monitoring. The authors present an adaptive critical path monitoring architecture which provides accurate and real-time measure of the processor's timing margin degradation. Special test patterns check a set of critical paths in the circuit-under-test. By activating the actual devices and signal paths used in normal operation of the chip, each test will capture up-to-date timing margin of these paths. The monitoring architecture dynamically adapts testing interval and complexity based on analysis of prior test results, which increases efficiency and accuracy of monitoring.

Provided by: University of Southern California Topic: Data Centers Date Added: Dec 2009 Format: PDF

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