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Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Previous work has shown that the criticality of instructions can be dynamically predicted with high accuracy, and that this information can be leveraged to optimize the performance of load value prediction and instruction steering for clustered architectures. In this work, the authors revisit the idea of criticality, but they propose several processor enhancements that can exploit criticality information and can be directly applied to modern x86 microarchitectures.
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