Date Added: Jan 2011
Interconnect delay dominates system delay in modern circuits, and with reduced feature sizes, coupling capacitance and signal crosstalk have become significant issues. By spacing interconnect wires effectively, and avoiding long parallel runs, coupling can be reduced; with current routing methods, however, this is difficult to achieve. This paper presents a new approach to area routing. Rather than inserting routes sequentially (Using a performance driven maze router), multiple candidate routes for each connection are generated; excess routes are then eliminated iteratively.