Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers
The SHA-3 competition organized by NIST has triggered significant efforts in performance evaluation of cryptographic hardware and software. These benchmarks are used to compare the implementation efficiency of competing hash candidates. However, such benchmarks test the algorithm in an ideal setting, and they ignore the effects of system integration. In this contribution, the authors analyze the performance of hash candidates on a high-end computing platform consisting of a multi-core Xeon processor with an FPGA-based hardware accelerator. They implement two hash candidates, Keccak and SIMD, in various configurations of multi-core hardware and multi-core software. Next, they vary application parameters such as message length, message multiplicity, and message source.