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Traditional memory systems based on memory technologies such as DRAM are fast approaching their cost and power limits. Alternative memory technologies such as Phase Change Memory (PCM) are being widely researched as a scalable, cost- and power-efficient alternative for DRAM. However, a PCM memory cell has a limited endurance of 107-108 writes, resulting in an ideal lifetime of only a few years which can be reduced further due to the non-uniform distribution of write traffic to the main memory. Wear leveling algorithms have been proposed to ensure uniform distribution of traffic to the main memory. However, this limited write endurance poses an easy to exploit loophole for attackers to bring the system down.
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