Design and Analysis of On-Chip Router for Network on Chip

Continuous scaling of CMOS technology makes it possible to integrate a large number of heterogeneous devices that need to communicate efficiently on a single chip. For this efficient routers are needed to takes place communication between these devices. This paper gives the design of on-chip routers based on optimizing power consumption and chip area. Proposed architecture of on-chip router in this paper give the results in which power consumption is reduced and silicon area is also minimize.

Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE) Topic: Mobility Date Added: Jan 2012 Format: PDF

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