Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA
In this paper the authors present the design and development of a high performance and low power MIPS microprocessor and implementation on FPGA. In this method they for achieving high performance and low power in the operation of the proposed microprocessor use different methods including, unfolding transformation (parallel processing), C-slow retiming technique, and double edge registers are used to get even reduce power consumption. Also others blocks designed based on high speed digital circuits. Because of feedback loop in the proposed architecture C-slow retiming can enhance designs that contain feedback loops.