Design and Implementation of 5 Stages Pipelined Architecture in 32 Bit RISC Processor
The proposed paper is the design of a 32 bit RISC (Reduced Instruction Set Computer) processor. The design will help to improve the speed of processor, and to give the higher performance of the processor. It has 5 stages of pipeline viz. instruction fetch, instruction decode, instruction execute, memory access and write back all in one clock cycle. The control unit controls the operations performed in these stages. All the modules in the design are coded in VHDL. Particular attention will be paid to the reduction of clock cycles as well as to improve the speed of processor.