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The technical manufacturing, which is based on Switch Fabric and VOQ (Virtual Output Queuing), is used in speedy routers, which are used in core network. For configuring of Switch Fabric having speedy scheduler with high Throughput is required. The most promising algorithm is iSLIP which is an iterative algorithm that provides high efficiency for best-effort traffic. In this paper the way of designing and implementing of Prioritized iSLIP algorithm on FPGA are described. Because of the simplicity of this algorithm in implementing and needlessly of this algorithm to high rate switches (Tera bps), this algorithm is a proper method for Scheduling.
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