Design and Implementation of a High Speed Clock and Data Recovery Delay Locked Loop Using SC Filter

In this paper, the authors present the design of a clock and data recovery circuit having a high data rate of 9.95328Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results, it is seen that the besides the conventional DLL circuit, the circuit using SC filter of fc

Provided by: Interscience Open Access Journals Topic: Hardware Date Added: Apr 2013 Format: PDF

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