Design and Implementation of a Latency Efficient Encoder for LTE Systems

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, the authors propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, Code Block (CB) segmentation, and a parallel processor, the authors are able to construct engines for turbo coding and rate matching of each CB in a parallel fashion.

Provided by: Electronics and Telecommunication Research Institute Topic: Mobility Date Added: Aug 2010 Format: PDF

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