Design and Implementation of DDA Architecture for FIR Filters
Traditionally, direct implementation of a K-tap FIR filter requires K Multiply-and-ACcumulate (MAC) blocks, which are expensive to implement in FPGA due to logic complexity and resource usage. To resolve this issue, the authors first present DA, which is architecture without multiplier. This paper implements the DA architecture. This architecture is applicable to only one type of filter co-efficient i.e. fixed filter co-efficient. In case, if they want to operate on variable filter co-efficient, they have been using Dynamic Distributed Arithmetic (DDA) architecture.