Design and Implementation of Hardware Based Complementary Vector Reduction for System-on-Chip (SoC)
Increase in the circuit density results in increase in test data volume which parallelly increases testing time and also results in excessive memory requirements. Test compression plays very important role in test data volume reduction mechanism which will reduce the test size without disturbing the system performance. Test data volume reduction in most cases is concerned with the scan based logic. A different approach of using complementary vector for test data volume reduction is proposed. Complementary vector can be found by complementing single or the whole bits. The complementary vector used implies that the tests applied will be twice, once in its original form and in complementary form.