Design and Implementation of High Performance AHB Arbiter for on Chip Bus Architecture

Resolution is a big issue in SOC (System On Chip) while dealing with number of master trying to sense a single data bus. The effectiveness of a system to resolve this priority resides in its ability to logical assignment of the chance to transmit data width of the data, response to the interrupts, etc. The purpose of this paper is to propose the scheme to implement such a system using the specification of AMBA bus protocol .The scheme involves the typical AMBA features of 'Single clock edge transition ', Split transaction ','Several bus masters ', 'Burst transfer '.The bus arbiter ensures that only one bus master at a time is allowed to initiate data transfers.

Provided by: International Journal of Engineering Science and Technology (IJEST) Topic: Mobility Date Added: Mar 2011 Format: PDF

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