Design and Implementation of Low Power Digital Fir Filter Based on Low Power Multipliers on Xilinx FPGA
All modules are realized using Verilog HDL. The functional verification of the all designs has been done by using Modelsim 10.1d tool. The synthesis and power analysis of all modules are done by using of Xilinx ISE 12.1. The methods to reduce dynamic power consumption of a digital FIR Filter of 16-tap multiplier these includes low power conventional multiplier, radix-4 booth's multiplier, Wallace tree multiplier, serial multiplier and shift/add multiplier and applied to FIR filters for low power consumption.