Design and Implementation of Low Power, High Speed and Area Efficient 8 Bit Multiplier Using M.G.D.I. Technique

In this paper, the authors have implemented radix-8 high speed low power binary multiplier using Modified Gate Diffusion Input (M.G.D.I) technique. Here, they have used "Urdhv Tiryakbhyam" (vertically and crosswise) algorithm because as compared to other multiplication algorithms it shows less computation and less complexity since it reduces the total number of partial products to half of it. This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design with new MGDI technique gives far better result in terms of area, switching delay and power dissipation.

Provided by: International Journal of Modern Engineering and Research Technology (IJMERT) Topic: Hardware Date Added: Oct 2014 Format: PDF

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