Design and Implementation of Multistage Interconnection Networks for SoC Networks
In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs, smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved. Each MIN can be considered as an alternative for a NoC architecture design for its simple topology and easy scalability with low degree. Multiprocessor systems are the only way to achieve high signal processing. The performance evaluation of such systems is dependent on the number of system processors and the access time of each processor to the processing unit. The processors get access to the memory unit through an interconnection network.