Design and Implementation of PLL Reconfiguration Using FPGA
A circuit to dynamically reconfigure the clock frequency of a synchronous digital system according to the changing needs of the application is described in this paper. This paper generally relates to phase locked loops and more particularly to reconfiguration of phase locked loops used for signal synchronization on integrated circuit chips. The circuit changes the clock frequency with a minimal time penalty and offers glitch free, reliable operation. The main characteristic of Reconfigurable Computing (RC) is the presence of hardware that can be reconfigured (ReconfigWare - RW) to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor.