Hardware

Design and Implementation of Viterbi Encoder and Decoder Using FPGA

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Executive Summary

In this paper, the authors present an implementation of the Viterbi algorithm using the Hardware Description Language and Implemented on FPGA. They begin with a description of the algorithm. Included are aspects of design specifications that must be considered when implementing the Viterbi algorithm as well as properties of Verilog HDL that can be used to simplify or optimize the algorithm. Finally, they evaluate the performance of the Viterbi algorithm implemented on FPGA. The Viterbi algorithm is a dynamic programming algorithm for finding the most likely sequence of hidden states - called the Viterbi path - that results in a sequence of observed events, especially in the context of Markov information sources, and more generally, hidden Markov models.

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