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Design and Modelling of Paralleled RAM Architecture

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Executive Summary

In this paper a structural approach to the design of Two-Dimensional (2D) addressing mode Static Random Access Memory (RAM) using Very High Speed Integrated Circuit Hardware Description Language (VHDL) has been proposed and successfully designed. The current inventiveness is to design and model in VHDL, a basic RAM unit of 1-bit per word comprising of 16 RAM cells (4?4 arrays) and 16 2D addressing lines. Four such RAM units are paralleled to 16 2D addressing lines in order to get four bits per word to form the desired memory structure.

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