Design and Simulation of an Efficient Vedic Booth Multiplier
A new multiplier design using the combination of modified booth's recoding algorithm and Vedic mathematics is presented in this paper. The basic Vedic multiplication algorithm requires multipliers to perform multiplication internally i.e, vertically and crosswise. If the authors use normal multipliers as an internal multiplier in Vedic its performance is high but it consumes much power. The proposed Vedic multiplier design uses modified booth's recoding algorithm to perform internal multiplication. The proposed multiplier design gives high performance and consumes less power.