Design and Simulation of FPGA based Digital System for Peak Detection and Counting
Field Programmable Gate Arrays (FPGAs) are especially popular for prototyping integrated circuits designs. This paper describes the simulation of peak detector and counter circuit based on FPGAs technology. Complete circuit was designed by writing appropriate program in Very high speed integrated circuit Hardware Description Language (VHDL) & ISE foundation 6.1. The designed system was simulated using Modelsim simulator SE. A maximum frequency of 190.513MHZ was reached with a minimum period of 5.249ns. 12 out of 3584 slices were used. The authors' system can be implemented on Xilinx Spartan 3 XC3S400-4pq208.