Design and Simulation of Pipelined Radix-2k Feed-Forward FFT Architectures

It is vital to develop a superior FFT processor to satisfy the necessities of real time and low price in several different systems. This paper discusses about the design of FFT processor using VHDL. Here the authors simulated the 64- point FFT processor with radix-4 in VHDL code using ModelSIM 6.5e and the synthesis was performed using Xilinx ISE 8.1i. The architectures of 32 point FFT with radix-2 and 64-point FFT with radix-4are shown in this paper. Finally the simulation graphs of pipelined 64-point FFT processor are generated.

Provided by: International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE) Topic: Hardware Date Added: Sep 2014 Format: PDF

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