Design and Verification of Performance of 32 Bit High Speed Truncation-Error -Tolerant Adder
In this paper, the authors have proposed an architecture for high speed Truncation Adder Algorithm. In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, Error Tolerance (ET), a novel Error-Tolerant Adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 74% improvement. One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.