Design and Verification of UART IP Core Using VMM
In the earlier era of electronics the UART (Universal Asynchronous Receiver/Transmitter) played a major role in data transmission. This UART IP CORE provides serial communication capabilities, which allow communication with modems or other external devices. This core is designed to be maximally compatible with industry standard designs. The key features of this design are WISHBONE INTERFACE WITH 8-BIT OR 32-BIT selectable data bus modes. Debug interface in 32-bit data bus mode. Register level and functional compatibility. FIFO operation. The design is verified using VMM based on system verilog. The test bench is written with regression test cases in order to acquire maximum functional coverage.