Design Approach for Fault Tolerance Algorithm in FPGA Architecture With BIST in Hardware Controller

Free registration required

Executive Summary

Redundancy based hardening techniques are applied at the pre-synthesis or synthesis level. To provide solutions for increasing the fault-tolerance capabilities with algorithms able to reduce sensitive configuration memory bits of FPGAs the authors use BIST method. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field.

  • Format: PDF
  • Size: 131 KB